library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity ALU is
    port (
        input1 : in std_logic_vector(7 downto 0);
        input2 : in std_logic_vector(7 downto 0);
        -- opcode : in std_logic_vector(7 downto 0);
        enable : in std_logic;
        output0 : out std_logic_vector(7 downto 0)
    );
end;

architecture behave of ALU is
begin
    process (input1, input2, enable)
    begin
        if enable = '1' then
            output0 <= input1 + input2;
        else
            output0 <= (others => 'Z');
        end if;
    end process;
end;
